1. Field of the Invention
The present invention relates to a method for resetting a plasma display panel, and more particularly, to a method for resetting the state of discharge cells of each of XY-electrode line pairs while a surface discharge type triode plasma display panel is driven by an address-while-display driving method.
2. Description of the Related Art
FIG. 1 shows the structure of a surface discharge type triode plasma display panel. FIG. 2 shows an example of a discharge cell of the plasma display panel shown in FIG. 1. Referring to FIGS. 1 and 2, address electrode lines A1, A2, . . . , Amxe2x88x921, Am, dielectric layers 11 and 15, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, phosphor layers 16, partition walls 17, and a magnesium oxide (MgO) layer 12 as a protective layer are provided between front and rear glass substrates 10 and 13 of a general surface discharge plasma display panel 1.
The address electrode lines A1 through Am are formed on the front surface of the rear glass substrate 13 in a predetermined pattern. A rear dielectric layer 15 is formed on the entire surface of the rear glass substrate 13 having the address electrode lines A1 through Am. The partition walls 17 are formed on the front surface of the rear dielectric layer 15 to be parallel to the address electrode lines A1 through Am. These partition walls 17 define the discharge areas of respective discharge cells and serve to prevent cross talk between discharge cells. The phosphor layers 16 are deposited between partition walls 17.
The X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn are formed on the rear surface of the front glass substrate 10 in a predetermined pattern to be orthogonal to the address electrode lines A1 through Am. The respective intersections define discharge cells. Each of the X-electrode lines X1 through Xn is composed of a transparent electrode line Xna (FIG. 2) formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode line Xnb (FIG. 2) for increasing conductivity. Each of the Y-electrode lines Y1 through Yn is composed of a transparent electrode line Yna (FIG. 2) formed of a transparent conductive material, e.g., ITO, and a metal electrode line Ynb (FIG. 2) for increasing conductivity. A front dielectric layer 11 is deposited on the entire rear surface of the front glass substrate 10 having the rear surfaces of the X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn. The protective layer 12, e.g., a MgO layer, for protecting the panel 1 against a strong electrical field is deposited on the entire surface of the front dielectric layer 11. A gas for forming plasma is hermetically sealed in a discharge space 14.
FIG. 3 shows a typical address-display separation driving method with respect to Y-electrode lines of the plasma display panel shown in FIG. 1. Referring to FIG. 3, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF1 through SF8. In addition, the individual subfields SF1 through SF8 are composed of address periods A1 through A8, respectively, and display periods S1 through S8, respectively.
During each of the address periods A1 through A8, display data signals are applied to the address electrode lines A1 through Am of FIG. 1, and simultaneously, a scan pulse is sequentially applied to the Y-electrode lines Y1 through Yn. If a high-level display data signal is applied to some of the address electrode lines A1 through Am while the scan pulse is applied, wall charges are induced from address discharge only in relevant discharge cells.
During each of the display periods S1 through S8, a display discharge pulse is alternately applied to the Y-electrode lines Y1 through Yn and the X-electrode lines X1 through Xn, thereby provoking display discharge in discharge cells in which wall charges are induced during each of the address periods A1 through A8. Accordingly, the brightness of a plasma display panel is proportional to a total length of the display periods S1 through S8 in a unit frame. The total length of the display periods S1 through S8 in a unit frame is 255T (T is a unit time). Accordingly, including a case where the unit frame is not displayed, 256 gray scales can be displayed.
Here, the display period S1 of the first subfield SF1 is set to a time 1T corresponding to 20. The display period S2 of the second subfield SF2 is set to a time 2T corresponding to 21. The display period S3 of the third subfield SF3 is set to a time 4T corresponding to 22. The display period S4 of the fourth subfield SF4 is set to a time 8T corresponding to 23. The display period S5 of the fifth subfield SF5 is set to a time 16T corresponding to 24. The display period S6 of the sixth subfield SF6 is set to a time 32T corresponding to 25. The display period S7 of the seventh subfield SF7 is set to a time 64T corresponding to 26. The display period S8 of the eighth subfield SF8 is set to a time 128T corresponding to 27.
Accordingly, if a subfield to be displayed is appropriately selected from among 8 subfields, a total of 256 gray scales including a gray level of zero at which display is not performed in any subfield can be displayed.
According to the above-described address-display separation display method, the time domains of the respective subfields SF1 through SF8 are separated, so the time domains of respective address periods of the subfields SF1 through SF8 are separated, and the time domains of respective display periods of the subfields SF1 through SF8 are separated. Accordingly, during an address period, an XY-electrode line pair is kept waiting after being addressed until all of the other XY-electrode line pairs are addressed. Consequently, in each subfield, an address period increases, and a display period decreases. As a result, the brightness of light emitted from a plasma display panel decreases. A method proposed for overcoming this problem is an address-while-display driving method as shown in FIG. 4.
FIG. 4 shows a typical address-while-display driving method with respect to the Y-electrode lines of the plasma display panel shown in FIG. 1. Referring to FIG. 4, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF1 through SF8. Here, the subfields SF1 through SF8 overlap with respect to the Y-electrode lines Y1 through Yn and constitute a unit frame. Since all of the subfields SF1 through SF8 exist at any time point, address time slots are set among display discharge pulses in order to perform each address step.
In each of the subfields SF1 through SF8, a reset step, address step, and display discharge step are performed. A time allocated to each of the subfields SF1 through SF8 depends on a display discharge time corresponding to a gray scale. For example, when displaying 256 gray scales with 8-bit video data in units of frames, if a unit frame (usually, {fraction (1/60)} second) is composed of 256 unit times, the first subfield SF1 driven according to video data of the least significant bit has 1 (20) unit time, the second subfield SF2 has 2 (21) unit times, the third subfield SF3 has 4 (22) unit times, the fourth subfield SF4 has 8 (23) unit times, the fifth subfield SF5 has 16 (24) unit times, the sixth subfield SF6 has 32 (25) unit times, the seventh subfield SF7 has 64 (26) unit times, and the eighth subfield SF8 driven according to video data of the most significant bit has 128 (27) unit times. Since the sum of unit times allocated to the subfields SF1 through SF8 is 255, 255 gray scale display can be accomplished. If a gray scale having no display discharge in any subfield is included, 256 gray scale display can be accomplished.
FIG. 5 shows a typical driving apparatus for the plasma display panel shown in FIG. 1. Referring to FIG. 5, the typical driving apparatus for the plasma display panel 1 includes a video processor 66, a logic controller 62, an address driver 63, an X-driver 64, and a Y-driver 65. The video processor 66 converts an external analog video signal into a digital signal to generate an internal video signal composed of, for example, 8-bit red (R) video data, 8-bit green (G) video data, 8-bit blue (B) video data, a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal. The logic controller 62 generates drive control signals SA, SY, and SX in response to the internal video signal from the video processor 66. The address driver 63 processes the address signal SA among the drive control signals SA, SY, and SX output from the logic controller 62 to generate a display data signal and applies the display data signal to address electrode lines. The X-driver processes the X-drive control signal SX among the drive control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to X-electrode lines. The Y-driver processes the Y-drive control signal SY among the drive control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to Y-electrode lines.
When an address-while-display driving method as shown in FIG. 4 is applied to the above-described driving of a plasma display panel, the brightness of light emitted from the plasma display panel can be increased, but it is not easy to perform reset while display pulses are periodically applied, which causes resetting performance to fall off.
For example, in a resetting process according to a conventional address-while-display driving method, a simple erasure discharge in which wall charges are erased from only cells in which display discharges have occurred in a previous subfield occurs. Accordingly, while space charges increase in the cells in which display discharges have occurred in a previous subfield, space charge decrease in cells in which display discharges have not occurred in the previous subfield. In this case, while the cells in which display discharges have occurred in a previous subfield can be selected by a relatively lower address voltage, the cells in which display discharges have not occurred can be selected by a relatively higher address voltage. Accordingly, address voltage and display voltage must be increased, which may badly affect the reliability and life of a plasma display apparatus. Moreover, display brightness is not uniform among the cells in which display discharges have occurred in a previous subfield and the cells in which display discharges have not occurred in the previous subfield, thereby degrading the display performance.
To solve the above-described problems, it is an object of the present invention to provide a resetting method capable of demonstrating high performance in driving a surface discharge type triode plasma display panel using an address-while-display driving method so that display performance can be increased and that address voltage and display voltage can be decreased, thereby improving the reliability and life of a plasma display apparatus.
To achieve the above object of the present invention, there is provided a resetting method for uniforming the state of discharge cells of each of XY-electrode line pairs while a positive voltage of a first level and a negative voltage of the first level are alternately applied to all X- and Y-electrode lines of a surface discharge type triode plasma display panel. The resetting method includes a line discharge step, an erasure step, and an iteration step.
The line discharge step is performed during a part of a first pulse width period during which the negative voltage of the first level is applied to all of the X-electrode lines, and simultaneously, the positive voltage of the first level is applied to all of the Y-electrode lines, since a second subfield corresponding to the first XY-electrode line pair starts after a first subfield corresponding to the first XY-electrode line pair ends. In the line discharge step, a negative voltage of a second level higher than the first level is applied to an X-electrode line of the first XY-electrode line pair, and simultaneously, a positive voltage of a third level higher than the first level is applied to a Y-electrode line of the first XY-electrode line pair, thereby provoking discharges in all discharge cells corresponding to the first XY-electrode line pair. In the erasure step, wall charges are erased from all of the discharge cells corresponding to the first XY-electrode line pair. In the iteration step, the line discharge step and the erasure step are repeated on the remaining XY-electrode line pairs.
According to the resetting method of the present invention, in the line discharge step, due to application of the negative voltage of the second level higher than the first level and the positive voltage of the third level higher than the first level, discharges are provoked in all of the discharge cells corresponding to the first XY-electrode line pair so that wall charges and space charges are satisfactorily formed. In the next erasure step, the wall charges are uniformly erased from all of the discharge cells corresponding to the first XY-electrode line pair, but the space charges still satisfactorily remain. Moreover, since the iteration step is performed, the line discharge step and the erasure step can be performed on each of the remaining XY-electrode line pairs while the positive voltage of the first level and the negative voltage of the first level are alternately applied to all of the X- and Y-electrode lines. As described above, since effective resetting adequate for an address-while-display driving method is performed, display performance increases. In addition, an address voltage and a display voltage are set to be low, thereby improving the reliability and the life of a plasma display apparatus.